This invention relates to a decimal multiplier device and method therefor.
An example of the conventional decimal multiplication method is indicated in FIG. 1. In this example a decimal multiplication is effected by using a register A storing a multiplier, a register C storing a multiplicand, two registers B and D, whose initial value is 0 and which store partial products, a multiplier decoder 3, which extracts one digit of the multiplier from the register A and controls an adder 1 and a gate 4, a shifter 2 and a selector 5. That is, on digit "n" of the content of the register A, i.e. the multiplier is extracted. The content X of the register B and the content of the register C, i.e. the multiplicand, multiplied by n are added by controlling the multiplier decoder 3 depending on n, and the result thus obtained is returned to the register B. This is the multiplication process for one digit, and multiplications for every digit of higher rank are effected successively. For this purpose digit shifts are effected according to the following procedure. The partial product for the one digit mentioned above is stored in the register B. This content is shifted by one digit (here one digit is represented by 4 bits) toward right by the shifter 2 (0 0 0 0 binary are filled in the leftmost digit). The result is set in the register B and the one digit pushed out from the right end is given at the left end of the shift register D, whose content is shifted by one digit toward right. That is, when the registers B and D are considered to be a series of registers, the whole is shifted by one digit toward right, the lower order digits in the partial product are stored in the register D and the higher order digits are stored in the register B. The multiplication process is effected by both the inner loop adding the multiplicand n times, where n is one digit extracted from the multiplier, and the outer loop repeating the shift described above for the succeeding digits and the product can be obtained in the registers B and D.
Further, in another example, when one digit extracted from the multiplier, n, is great (e.g. equal to or greater than 6), the multiplicand Y is subtracted (10-n) times from the content X of the register B representing the higher order digits of the partial product and in the addition subtraction loop for the digit which is higher by 1 than the current digit, addition is performed once more (or subtraction is performed once less). This method, by which the number of additions/subtractions is reduced as a whole in order that operation speed is increased, is widely utilized.
As described above, in the decimal multiplication method indicated in FIG. 1, there are following problems preventing the speed-up of the operation.
(i) The operation is implemented by the two loops, i.e. the inner loop for addition/subtraction and the outer loop for shifting every digit, and these procedures in the different loops are performed separately. PA1 (ii) Since the partial products obtained in the course of an operation are stored in the register B and the register D in a divided manner in the shifting of every digit, it is necessary to use a register which is twice as long as the ordinary register (that is, the registers B and D should be considered as a series of registers). PA1 (iii) Since the final result i.e. the product is obtained in the register B and the register D separately, two parts sould be combined in one result and thus many subsequent procedures are necessary after the product has been calculated.